1. Field of the Invention
The embodiments discussed herein are related to a level shift circuit.
2. Background of the Related Art
In a half-bridge circuit that is driven by a high-potential power supply, the switching elements on the high side and the low side that are connected in series are driven by driving circuits that have different reference potentials. A high voltage driver integrated circuit (or “HVIC”) is known as a high-side driving circuit. In an HV driver IC, since a signal which has been generated with the low-side ground potential as a reference is not directly usable as the signal that switches the high-side switching element on or off, the signal is used after its level has been shifted by a level shift circuit (see, for example, Japanese Patent No. 5,402,852 (Paragraphs [0120] to [0133], FIG. 15) and Japanese Patent No. 5,354,417 (Paragraphs [0033] to [0041], FIG. 1)). The level shift circuits disclosed in Japanese Patent No. 5,402,852 and Japanese Patent No. 5,354,417 will now be described in order.
FIG. 5 depicts an example configuration of a half-bridge circuit that uses a conventional level shift circuit.
In FIG. 5, a high-side switching element XD1 and a low-side switching element XD2 are connected in series to construct an output circuit 100 that has a high-voltage power supply E (whose voltage is also indicated hereinafter as “E”) connected to both ends. Here, in the illustrated example, N-channel power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are used as the switching elements XD1 and XD2.
This half-bridge circuit is configured so that the high-side switching element XD1 is controlled by an output signal HO of a high-side driving circuit 110 and the low-side switching element XD2 is controlled by an output signal LO of a low-side driving circuit 120.
The high-side driving circuit 110 is equipped with a high-side driver 111 that drives the switching element XD1, a power supply E1 (whose voltage is also indicated hereinafter as “E1”), and a level shift circuit of the other component elements.
The level shift circuit includes a series circuit of a level shift resistor LSR1 and an N-channel MOSFET high breakdown voltage transistor HVN1 and a series circuit of a level shift resistor LSR2 and an N-channel MOSFET high breakdown voltage transistor HVN2. These series circuits are connected at one end to a power supply line VB (whose potential is also indicated hereinafter as “VB”) that is connected to a high potential-side terminal of the power supply E1 and at another end to ground potential (GND) that is the low-side reference potential. A set signal SET that indicates start timing of an on period of the switching element XD1 is inputted into the gate of the high breakdown voltage transistor HVN1. A reset signal RSET that indicates end timing of the on period of the switching element XD1 is inputted into the gate of the high breakdown voltage transistor HVN2. Note that the capacitors connected between the sources and drains of the high breakdown voltage transistors HVN1 and HVN2 indicate the parasitic capacitances Cds1 and Cds2 of the high breakdown voltage transistors HVN1 and HVN2.
A junction setdrn (whose signal is also indicated hereinafter as the “set drain signal setdrn”) between the level shift resistor LSR1 and the high breakdown voltage transistor HVN1 is connected to a latch malfunction protection circuit 112. The junction resdrn between the level shift resistor LSR2 and the high breakdown voltage transistor HVN2 (whose signal is also indicated hereinafter as the “reset drain signal resdrn”) is also connected to the latch malfunction protection circuit 112. Here, the latch malfunction protection circuit 112 operates so as to pass the set drain signal setdrn and the reset drain signal resdrn without amendment only when one out of the junctions setdrn and resdrn is at an L level and the other junction is at an H level.
The outputs of the latch malfunction protection circuit 112 are connected to a latch circuit 113, and the output of the latch circuit 113 is connected to the high-side driver 111. The output of the latch circuit 113 is also connected to the input of an inverter circuit INV1 and the output of the inverter circuit INV1 is connected to an input of an inverter circuit INV2. The output of the inverter circuit INV1 is also connected to one end of a series circuit of a resistor R11 and a resistor R12, and the other end of this series circuit is connected to the junction setdrn. A midpoint between the resistor R11 and the resistor R12 is connected to the gate of a P-channel MOSFET transistor PM2 connected in parallel to the level shift resistor LSR2. The output of the inverter circuit INV2 is connected to one end of a series circuit of a resistor R13 and a resistor R14, and the other end of this series circuit is connected to the junction resdrn. A midpoint between the resistors R13 and the resistor R14 is connected to the gate of a P-channel MOSFET transistor PM1 connected in parallel to the level shift resistor LSR1.
The level shift circuit also includes diodes D1 and D2 whose anodes are connected to a junction VS (whose potential is hereinafter also indicated as the “high-side reference potential VS”) between the switching element XD1 and the switching element XD2. The cathode of the diode D1 is connected to the junction setdrn and the cathode of the diode D2 is connected to the junction resdrn. The diodes D1, D2 are provided to clamp the voltages of the junctions setdrn and resdrn so as not to exceed the high-side reference potential VS and so prevent an overvoltage from being inputted into the latch malfunction protection circuit 112.
The low-side driving circuit 120 includes a low-side driver 121 that drives the switching element XD2 and a power supply E2. The low-side driver 121 is supplied with power from the power supply E2, inputs a low-side control signal, and outputs the output signal LO for on/off driving of the switching element XD2.
One end of a load L is connected to the junction VS between the switching element XD1 and the switching element XD2 of the output circuit 100, that is, to a power supply line that is at the high-side reference potential, and the other end of the load L is connected to the ground potential (GND) that is the reference potential of the low-side driving circuit 120.
For a half-bridge circuit like this, consider a case where there is a switch from a state where the low-side switching element XD2 is on to a state where the high-side switching element XD1 is on.
When the low-side switching element XD2 is turned off and the high-side switching element XD1 is turned on, the high-side reference potential VS of the junction VS switches suddenly from the ground potential to the high voltage E. Due to this, the voltage E1 of the power supply E1 is added to the potential VB of the power supply line VB of the high-side driving circuit 110, so that the voltage relative to the ground potential is (E+E1). At this time, when the high breakdown voltage transistors HVN1 and HVN2 are off, the potential VB is applied via the level shift resistors LSR1 and LSR2 to both the junctions setdrn and resdrn. Since the two input signals are both H-level signals, the latch malfunction protection circuit 112 blocks the passage of the set drain signal setdrn and the reset drain signal resdrn, so that the latch circuit 113 is kept in a state where the high-side switching element XD1 is turned on.
However, since the high breakdown voltage transistors HVN1 and HVN2 have the respective parasitic capacitances Cds1 and Cds2, so-called CR circuits are formed by the level shift resistors LSR1 and LSR2 and the parasitic capacitances Cds1 and Cds2. Since the voltage (E+E1) is applied to these CR circuits, until the parasitic capacitances Cds1 and Cds2 become completely charged, an error signal called “dV/dt noise” or “switching noise” is superimposed on the junctions setdrn and resdrn.
During charging of the parasitic capacitances Cds1 and Cds2, the potentials of the junctions setdrn and resdrn are at the L level, and since both input signals are at the L level, the latch malfunction protection circuit 112 will block passage of the set drain signal setdrn and the reset drain signal resdrn. However, there is a tendency for the magnitudes of the parasitic capacitances Cds1 and Cds2 to differ due to manufacturing variations. When the difference in magnitudes is relatively large, the timing at which the potentials of the junctions setdrn and resdrn change from the L level to the H level will differ, which results in the latch malfunction protection circuit 112 passing the set drain signal setdrn or the reset drain signal resdrn. In addition, when “V(t)” is the voltage applied to the CR circuit, “Vx” is the voltage at the CR junction, and k is the gradient of the rise in V(t), the magnitude of the dV/dt noise on the high side is expressed asV(t)−Vx=kCR(1−exp(−t/CR))(see, for example, Expression (13) in Japanese Patent No. 5,402,852). From this expression, the larger the capacitance and resistance of the level shift circuit, and the more sudden the change in Vx, the larger the dV/dt noise. It is therefore understood that the larger the difference in magnitude between the parasitic capacitances Cds1 and Cds2, the greater the influence of this difference. Accordingly, when the difference in magnitude between the parasitic capacitances Cds1 and Cds2 is large, this results in the same operation being performed as when the set signal SET or the reset signal RSET is inputted, which leads to the half-bridge circuit malfunctioning.
To eliminate such malfunctioning, the resistances of the level shift resistors LSR1 and LSR2 are varied in keeping with the state of the output signal of the latch circuit 113 in a direction where the state of the output signal of the latch circuit 113 is maintained. That is, when the output signal of the latch circuit 113 is at the H level, an L level that has been inverted by the inverter circuit INV1 is applied to the resistor R11. Since this L level of the output of the inverter circuit INV1 is equal to the high-side reference potential VS, the gate voltage of the transistor PM2 is pulled down, which places the transistor PM2 in an on state. At the same time, an H level produced by further inversion by the inverter circuit INV2 is applied to the resistor R13. Since this H level of the output of the inverter circuit INV2 is equal to the potential VB, the gate voltage of the transistor PM1 is pulled up, which places the transistor PM1 in an off state. Due to this, (combined resistance of the level shift resistor LSR1 and the resistance between the source and drain of the transistor PM1)>(combined resistance of the level shift resistor LSR2 and the on resistance of the transistor PM2), so that even when dV/dt noise is produced, the potential of the reset drain signal resdrn is unlikely to fall compared to the potential of the set drain signal setdrn. Out of these potentials, since it is the set drain signal setdrn that is likely to individually fall to the L level due to the dV/dt noise, a situation where the latch circuit 113 is erroneously reset and the state of the output signal changes is avoided. Note that the on resistance (impedance) of the transistor PM2 that forms a combined resistance with the level shift resistor LSR2 is decided by the ratio of the resistances of the resistor R11 and the resistor R12. When the output signal of the latch circuit 113 is at the L level, conversely the set drain signal setdrn becomes unlikely to fall, so that a situation where the latch circuit 113 is erroneously set and the state of the output signal changes is avoided.
FIG. 6 depicts another example configuration of a half-bridge circuit that uses a conventional level shift circuit. In FIG. 6, component elements that are the same as or the equivalents of the component elements depicted in FIG. 5 have been assigned the same reference numerals and detailed description thereof is omitted.
The level shift circuit depicted in FIG. 6 includes a logical OR circuit OR1 and P-channel MOSFET transistors PM3 and PM4 that are connected in parallel to the level shift resistors LSR1 and LSR2. The inputs of the logical OR circuit OR1 are connected to the junctions setdrn and resdrn of the level shift outputs and the output of the logical OR circuit OR1 is connected to the gates of the transistors PM3 and PM4.
Here, in a state where the low-side switching element XD2 is off, the high-side switching element XD1 is on, and the potential VB of the power supply line VB rises, when the high breakdown voltage transistors HVN1 and HVN2 are off, the potentials of the junctions setdrn and resdrn fall due to the presence of the parasitic capacitances Cds1 and Cds2 of the high breakdown voltage transistors HVN1 and HVN2. On detecting that the potentials of both junctions setdrn and resdrn have dropped below a logical threshold, the logical OR circuit OR1 outputs an L level, and the transistors PM3 and PM4 connected in parallel to the level shift resistors LSR1 and LSR 2 turn on.
By doing so, the potentials of the junctions setdrn and resdrn are both pulled up to the H level. Although detailed description is omitted here, with this configuration, when dV/dt noise occurs in a state where there is a difference in magnitude between the parasitic capacitances Cds1 and Cds2, a junction out of the junctions setdrn and resdrn into which a regular signal is inputted will become the L level or both junctions will become the L level or the H level, so that a situation where the latch circuit 113 is erroneously set or reset is avoided.
Although the high-side reference potential VS rises when the low-side switching element XD2 is off and the high-side switching element XD1 switches from the off state to the on state, aside from this, there are also other situations where the high-side reference potential VS rises. One example is a case where the load L is an inductive load and a current that flows from the load L into the output circuit 100 is not capable of being quickly cut off during the dead time where both of the switching elements XD1 and XD2 are off. In this case, the current that has flowed into the output circuit 100 from the load L charges the stray capacitance of the line at the high-side reference potential VS, so that the high-side reference potential VS rapidly rises and dV/dt noise occurs. Compared to dV/dt noise that is generated momentarily when the high-side switching element XD1 is switched from an off state to an on state, it is common for this type of dV/dt noise to be sustained for long time by the load L.
However, since the level shift circuits in FIGS. 5 and 6 give no consideration to the application of dV/dt noise to the junction VS for an extended period, it has been confirmed that when dV/dt noise is applied for an extended period, malfunctioning may occur due to the influence of manufacturing variations in the parasitic capacitances Cds1 and Cds2. In an example state where the magnitude of the parasitic capacitance Cds2 is smaller than the magnitude of the parasitic capacitance Cds1, it is believed that when the difference in the influence of the dV/dt noise expressed by the equation V(t)−Vx=kCR(1−exp(−t/CR)) between the junction resdrn and the junction setdrn is larger than the effect of the circuitry provided as a countermeasure, the potential of the junction resdrn will rise, as time passes the potential of the junction resdrn will reach the H level before the junction setdrn, the condition that protects the latch will be removed, and the latch will be erroneously set, resulting in the switching element XD1 being turned on.